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SAN JOSE - Cadence Design Systems, Inc. (NASDAQ:CDNS), a $97.3 billion market cap technology leader with impressive gross profit margins of 85.6%, announced advancements in chip design automation and intellectual property development through its collaboration with Taiwan Semiconductor Manufacturing Company (TSMC), according to a press release issued Wednesday. According to InvestingPro data, Cadence maintains excellent financial health with strong revenue growth of 22.3% over the last twelve months.
The companies have expanded their partnership to support TSMC’s advanced process nodes, including N3, N2, and A16 technologies. Cadence’s AI design flows for chip and 3D-IC are now available for these process technologies and for new features in TSMC’s 3DFabric packaging platform.
Additionally, Cadence is working with TSMC on electronic design automation (EDA) flow development for TSMC’s A14 process, with the first process design kit scheduled for release later this year.
The collaboration includes AI-driven design solutions that enable chip development with optimized power, performance, and area in TSMC’s N2 process. TSMC has validated new AI features such as automated design rule check violation fixing assistance to accelerate design closure.
Cadence has also introduced silicon-proven IP on TSMC’s N3P process technology, including the first HBM4 IP, LPDDR6/5X memory interfaces at 14.4G, and DDR5 12.8G MRDIMM Gen2 IP. For connectivity, Cadence offers PCI Express 7.0 IP with 128GT/s and 224G SerDes capabilities.
"We’re helping designers develop the next generation of AI and HPC by supporting TSMC’s leading technologies with AI features, IP and beyond," said Chin-Chi Teng, senior vice president and general manager of Cadence’s Digital and Signoff Group, in the press release.
The partnership aims to address challenges in semiconductor development for artificial intelligence and high-performance computing applications, focusing on performance and energy efficiency improvements.
In other recent news, Cadence Design Systems announced a definitive agreement to acquire Hexagon AB’s Design & Engineering business for approximately €2.7 billion. The transaction involves a payment structure of 70% in cash and 30% in Cadence common stock, with an expected closing in the first quarter of 2026. Cadence also completed its acquisition of the Arm Artisan foundation IP business, enhancing its design IP portfolio and strengthening its system-on-chip design capabilities. Additionally, Cadence unveiled a new Dynamic Power Analysis App for AI chip design, developed in collaboration with NVIDIA, offering high accuracy in power analysis for complex AI designs.
In terms of analyst activity, Stifel reiterated its Buy rating and $395 price target on Cadence, citing the company’s role in AI-first silicon and system design. Berenberg raised its price target to $400, maintaining a Buy rating following Cadence’s strong second-quarter earnings report. These developments reflect Cadence’s continued growth and strategic initiatives in advanced technology sectors.
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