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SEALSQ Corp (LAES) completed validation of its QS7001 quantum-resistant hardware platform’s cryptographic toolbox, according to a company statement. The semiconductor developer said the chip will be available to customers in the fourth quarter of 2025.
The validation confirms performance of post-quantum cryptographic algorithms including Kyber and Dilithium alongside supporting hardware components. SEALSQ has begun the Common Criteria EAL5+ certification process with Serma labs and made the platform available for early adopters to integrate with their firmware.
The QS7001 is built on a RISC-V architecture and implements NIST-standardized algorithms designed to counter quantum computing attacks. The platform features hardware accelerators for cryptographic functions, low-power design for IoT devices, and tamper-resistant security modules.
The company targets applications in smart meters, automotive electronic control units, and medical devices. Expected benefits include protection against quantum attacks, compact integration capabilities, and compliance with the EU Cyber Resilience Act requirements for connected devices.
SEALSQ is developing the QVault TPM, a Trusted Platform Module integrating TPM 2.0 functionality on the QS7001 platform. The QVault TPM is undergoing Common Criteria certification and is planned for launch in the first half of 2026, pending certification by the Trusted Computing Group.
"We’re excited to validate the QS7001 and move toward certification, keeping us ahead in the quantum race," said Jean Pierre Enguent, CTO of SEALSQ. "With breakthroughs like Rigetti’s new chip pushing quantum computing forward, our QS7001 and QVault TPM enable device makers to implement the security they need to stay protected, compliant and competitive."
The Geneva-based company develops semiconductors, public key infrastructure, and post-quantum technology hardware and software products.